TABLE OF CONTENTS CHAPTER 1INTRODUCTION TO THE INTEL ARCHITECTURE MMX TECHNOLOGY 1.1.ABOUT THE INTEL ARCHITECTURE MMX TECHNOLOGY1-1 1.1.1. Single Instruction, Multiple Data (SIMD) Technique1-1 1.1.2. Performance Improvement1-2 1.2.ABOUT THIS MANUAL1-2 1.3.RELATED DOCUMENTATION1-3 CHAPTER 2INTEL ARCHITECTURE MMX TECHNOLOGY FEATURES 2.1.NEW FEATURES2-1 2.2.NEW DATA TYPES2-1 2.3.MMX Technology REGISTERS2-2 2.4.EXTENDED INSTRUCTION SETv2-3 2.4.1. Packed Data2-3 2.4.2. Saturation Arithmetic Vs. Wrap Around2-4 2.4.3. Instruction Group Overview2-5 2.4.3.1. ARITHMETIC INSTRUCTIONS2-5 2.4.3.2. COMPARISON INSTRUCTIONS2-6 2.4.3.3. CONVERSION INSTRUCTIONS2-6 2.4.3.4. LOGICAL INSTRUCTIONS2-6 2.4.3.5. SHIFT INSTRUCTIONS2-7 2.4.3.6. DATA TRANSFER INSTRUCTIONS2-7 2.4.3.7. EMMS (EMPTY MMX TECHNOLOGY STATE) INSTRUCTION2-7 2.4.4. Instruction Operand2-7 2.5.COMPATIBILITY2-8 CHAPTER 3APPLICATION PROGRAMMING MODEL 3.1.DATA FORMATS3-1 3.1.1. Memory Data Formats3-1 3.1.2. IA MMX Technology Register Data Formats3-2 3.1.3. IA MMX Technology Instructions and the Floating-Point Tag Word3-2 3.2.PREFIXES3-3 3.3.WRITING APPLICATIONS WITH IA MMX TECHNOLOGY CODE3-3 3.3.1. Detecting IA MMX Technology Existence Using the CPUID Instruction3-3 3.3.2. The EMMS Instruction3-4 3.3.3. Interfacing with IA MMX Technology Procedures and Functions3-5 3.3.4. Writing Code with IA MMX Technology and Floating-Point Instructions3-5 3.3.4.1. RECOMMENDATIONS AND GUIDELINES3-6 3.3.5. Multitasking Operating System Environment3-7 3.3.5.1. COOPERATIVE MULTITASKING OPERATING SYSTEM3-7 3.3.5.2. PREEMPTIVE MULTITASKING OPERATING SYSTEM3-7 3.3.6. Exception Handling in IA MMX Technology Application Code3-8 3.3.7. Register Mapping3-8 CHAPTER 4SYSTEM PROGRAMMING MODEL 4.1.CONTEXT SWITCHING4-1 4.1.1. Cooperative Multitasking Operating System4-1 4.1.2. Preemptive Multitasking Operating System4-1 4.2.EXCEPTIONS4-3 4.3.COMPATIBILITY WITH EXISTING SOFTWARE ENVIRONMENTS4-4 4.3.1. Register Aliasing4-4 4.3.2. The Effect of Floating-Point and MMX Technology Instructions on the Floating-Point Tag Word4-7 4.3.2.1. ALIASING SUMMARY4-8 4.3.3. Context Switch Support4-8 4.3.4. Floating-Point Exceptions4-8 4.3.5. Debugging4-9 4.3.6. Emulation of the Instruction Set4-9 4.3.7. Exception handling in Operating Systems4-9 CHAPTER 5INTEL ARCHITECTURE MMX TECHNOLOGY INSTRUCTION SET 5.1.INSTRUCTION SYNTAX5-1 5.2.INSTRUCTION FORMAT5-2 5.3.NOTATIONAL CONVENTIONS5-3 5.4.HOW TO READ THE INSTRUCTION SET PAGES5-4 EMMS--Empty MMX Technology State5-8 MOVD--Move 32 Bits5-10 MOVQ--Move 64 Bits5-12 PACKSSWB/PACKSSDW--Pack with Signed Saturation5-14 PACKUSWB--Pack with Unsigned Saturation5-16 PADDB/PADDW/PADDD--Packed Add5-18 PADDSB/PADDSW--Packed Add with Saturation5-21 PADDUSB/PADDUSW--Packed Add Unsigned with Saturation5-23 PAND--Bitwise Logical And5-26 PANDN--Bitwise Logical And Not5-28 PCMPEQB/PCMPEQW/PCMPEQD--Packed Compare for Equal5-30 PCMPGTB/PCMPGTW/PCMPGTD--Packed Compare for Greater Than5-33 PMADDWD--Packed Multiply and Add5-36 PMULHW--Packed Multiply High5-38 PMULLW--Packed Multiply Low5-40 POR--Bitwise Logical Or5-42 PSLLW/PSLLD/PSLLQ--Packed Shift Left Logical5-44 PSRAW/PSRAD--Packed Shift Right Arithmetic5-47 PSRLW/PSRLD/PSRLQ--Packed Shift Right Logical5-50 PSUBB/PSUBW/PSUBD--Packed Subtract5-53 PSUBSB/PSUBSW--Packed Subtract with Saturation5-56 PSUBUSB/PSUBSW--Packed Subtract Unsigned with Saturation5-58 PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ--Unpack High Packed Data5-60 PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ--Unpack Low Packed Data5-63 PXOR--Bitwise Logical Exclusive OR5-66 APPENDIX AIA MMX TECHNOLOGY INSTRUCTION SET SUMMARY APPENDIX BIA MMX TECHNOLOGY INSTRUCTION FORMATS AND ENCODINGS APPENDIX CALPHABETICAL LIST OF IA MMX TECHNOLOGY INSTRUCTION SET MNEMONICS APPENDIX DIA MMX TECHNOLOGY INSTRUCTION SET OPCODE MAP Figures FigureTitlePage 2-1.Packed Data Types2-2 2-2.MMX Technology Register Set2-3 3-1.Eight Packed Bytes in Memory (at address 1000H)3-2 4-1.Example of FP and MMX Technology State Saving in Operating System4-2 4-2.Aliasing of MMX Technology to Floating-Point Registers4-5 4-3.Mapping of MMX Technology Registers to Floating Point Registers4-6 5-1.Floating Point Tag Word Format5-8 B-1.Key to Codes for Datatype Cross-ReferenceB-3 Tables TableTitlePage 2-1.Data Range Limits for Saturation2-4 3-1.IA MMX Technology Instruction Behavior with Prefixes Used by Application Programs3-3 4-1.Effect of the FP and MMX Technology Instructions on the FP Tag Word4-7 4-2.Effects of MMX Technology Instruction on FP State4-8 A-1.IA MMX Technology Instruction Set Summary, Grouped into Functional CategoriesA-2 B-1.Encoding of Granularity of Data (gg) FieldB-1 B-2.Encoding of 32-bit General Purpose (reg) Field for Register-to-Register OperationsB-2 B-3.Encoding of 64-bit MMX Technology Register (mmxreg) FieldB-2 B-4.IA MMX Technology Instruction Formats and EncodingsB-3 C-1.IA MMX Technology Instruction Set MnemonicsC-1 D-1.Opcode Map (First Byte is 0FH)D-3 D-2.Opcodes Determined by Bits 5, 4, 3 of Mod R/M ByteD-5 Examples ExampleTitlePage 3-1.Partial sequence of IA MMX technology detection by CPUID3-4 3-2.Floating-point and MMX Technology Code3-7